MODES · Monolithic Optoelectronic Devices on Silicon

Monolithic Optoelectronic Devices on Silicon

Nowadays, microelectronics set the pace for the whole knowledge-based economy and society in terms of the ever-rising demand for mobile devices and the exponentially growing internet data transfer. However, the widening gap between the increasing number of transistors on a single Si chip and the delivered performance indicates the approaching limits of classical device scaling. Additionally, this miniaturization results in severe energy dissipation in the interconnection of devices. A smart way to overcome this emerging power consumption crisis is to avoid heating by replacing the on-chip and/or chip-to-chip electrical interconnects with optical interconnects. Due to their direct bandgap, III-V compounds are ideal for the integration of photonics with Si-based electronics on the very same chip. This would enable large-scale optoelectronics integration hindered so far by coupling- and overlay issues introduced by state-of-the-art III-V bonding on Silicon. The foreseen impact of MODES on the European excellence and competitiveness is manifold: - Impact in Science and Technology would be tremendous if it is possible to overcome the present limitations in local self-aligned III-V integration on Si. Naturally, this will be an enabler for photonic interconnects, which is the prime focus of MODES. - Europe has a strong research community and approx. 5000 SMEs active in Photonics, hence, breakthroughs achieved within MODES would contribute to the development of new applications within this field, thus, to the growth of the respective industries in Europe. In MODES, a solution for III-V optoelectronic integration on Si is addressed by extending a novel approach developed at IBM (Template-Assisted Selective Epitaxy) for III-V transistors to the realization of optical devices. The focus of MODES is to develop and investigate this novel approach for self-aligned monolithic integration of active and passive III-V optoelectronic devices on a Silicon platform. It targets on the optimization of GaAs- and InP-based III-V growth within customized oxide templates. Moreover, this research aims at designing and fabricating doped, defect-free III-V heterostructures for electrically-driven optoelectronic devices integrated on Si. We pursued three scientific and technical objectives such as (1) the growth and integration of III-V material with silicon-on-insulator waveguides, (2) the design and fabrication of passive and active photonic devices based on integrated III-V materials and Si waveguides and (3) the optical and electrical characterization of the photonic components. Moreover, we identified six aims; (i) to design and fabricate oxide templates suitable for the defect-free epitaxial growth of III/V compounds directly on Silicon-On-Insulator (SOI) wafers, (ii) to optimize and characterize the GaAs- and InP-based III/V growth within the oxide templates developed in Aim 1, (iii) to engineer and grow defect-free III/V heterostructures in order to confine charge carriers for efficient light emission and detection, (iv) to fabricate controlled n- and p-type doped sections for the realization of electrically actuated light emitters and detectors, (v) to design, fabricate and optically characterize suitable waveguide geometries, the implementation of grating couplers and cavity designs based on heterostructures developed in Aim 3 and (vi) to obtain a full electrical and optical characterization of the developed and integrated III/V optoelectronic devices. This report will cover the progress made in the first year of the project, focusing on the development and fabrication of suitable oxide templates as well as the monolithic integration of defect-free III-V materials on Si(001) and optical characterization.

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