H2020Individual fellowship2016–2018

FPGA Accelerators · Energy Efficient FPGA Accelerators for Graph Analytics Applications

Horizon 2020 — Marie Skłodowska-Curie Actions

Duration: 2016-04-01 → 2018-03-31
EU contribution: €145,846
Participants: 1
Scheme: MSCA-IF-EF-ST

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Results in brief

Energy Efficient FPGA Accelerators for Graph Analytics Applications

It is reported that data centers today consume significant portion of the global electricity usage. This is expected to increase in the upcoming years as the amount of data processed in the cloud increases substantially. An effective way for data centers to achieve better performance and energy efficiency is to perform computation on specialized processing elements. Field programmable gate arrays (FPGAs) enable customization of logic after manufacturing to achieve better energy efficiency compared to general purpose processors. Today, prominent hardware and software companies are investing in data center solutions that integrate FPGAs with CPUs, and significant performance and energy improvements have been demonstrated for several data center applications. However, the main barrier for wide spread adoption of FGPAs in data centers is the cost of programming, which typically requires months of development time by hardware engineers. The objective of this project is to lower this barrier for emerging graph applications. The basic idea is to use an abstract interface that allows a domain expert to describe an application as a set of functions defined per vertex and/or edge. We have developed a customizable implementation template that allows users to specify C++ functions to describe different graph applications. The developed template hides from users many low-level implementation details such as parallelization, pipelining, synchronization, memory access optimization, race and deadlock avoidance. This helps bridge the gap between high level application descriptions and costly hardware implementations. Our experiments show that the accelerators developed using the proposed template can lead to significant energy efficiency improvements compared to multi-core server CPUs.

Data: CORDIS, © European Union

Project objective

It is reported that data centers today consume up to 3 percent of the global electricity usage. This is expected to increase in the upcoming years as the amount of data processed in the cloud increases substantially. An effective way for data centers to achieve better performance and energy efficiency is to perform computation on specialized processing elements. Field programmable gate arrays (FPGAs) enable customization of logic after manufacturing to achieve better energy efficiency compared to general purpose processors. Today, prominent hardware and software companies are investing in data center solutions that integrate FPGAs with CPUs, and significant energy consumption and performance improvements have been demonstrated for several data center applications. However, the main barrier for wide spread adoption of FGPAs in data centers is the cost of programming, which typically requires months of development time by hardware designers. This makes it unaffordable for small-to-medium software companies to effectively utilize the available FPGAs. The purpose of this project is to lower this barrier for emerging graph analytics applications for knowledge discovery and machine learning. The basic idea is to use an abstract interface that allows a domain expert to describe an application as a set of serial functions defined per vertex and/or edge. We propose a customizable implementation template that automatically maps the abstract user functions to massively parallel FPGA implementations. The proposed template will hide from users many low level implementation details such as parallelization, pipelining, synchronization, memory access optimization, race and deadlock avoidance, etc. This will help bridge the gap between high level application descriptions and costly hardware implementations. Our preliminary architecture simulations have shown that the proposed graph processors can achieve significantly better energy efficiency than general purpose processors.

Original text from CORDIS.

Participants

BILKENT UNIVERSITESI VAKIF · Bilkent AnkaraCoordinatorTürkiye

FPGA Accelerators · Energy Efficient FPGA Accelerators for Graph Analytics Applications

Results in brief

Energy Efficient FPGA Accelerators for Graph Analytics Applications

Project objective

Participants

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