ULKCOND · Zero damage Ultra-Low-K etch using the precursor CONDensation technique
Horizon 2020 — Marie Skłodowska-Curie Actions
- Duration
- 2016-04-01 → 2018-03-31
- EU contribution
- €160,800
- Participants
- 1
- Scheme
- MSCA-IF-EF-ST
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Results in brief
Zero damage Ultra-Low-K etch using the precursor CONDensation technique
Since the beginning of the 21st century, the scaling down in micro-electronics is impacted by the RC delay: the average time of transport of the electrons between two transistors is too long. A possible solution to this problem is to reduce the capacitance (C) value of the circuit connecting various active components (the interconnects). This is done by reducing the permittivity (k) of the dielectric present in between the metal wires. The emergent material family to replace the (dense) SiO2 is the porous organo-silicate glass (p-OSG). These compounds are porous, SiOCH-based and with methyl (Si-CH3) terminations. They show low-k value (k < 2.3 vs 4.2 for SiO2) and good mechanical properties (Young modulus ≈ 6 GPa). However, the integrations steps required to fabricate the interconnects are detrimental for both electrical and mechanical properties of the p-OSG. The ULKCOND project (for zero damage Ultra-Low-K etch using the precursor CONDensation technique) aimed at protecting the dielectric from damage during the plasma etching step (in-situ). The goal is to use micro-capillary condensation to condensate a gas into the porous low-k, without condensing on the surface. The condensation precursor are used together with other gases to etch the low-k. Because the pores are filled with a liquid/solid phase during the etch process, the methyl groups are expected to be protected from the plasma’s reactive radicals and VUV emission. The low-k protection during critical steps (like etching) is of main importance for the scaling of future CMOS devices. ULKCOND has demonstrated that the cryo-etching is protecting very well the low-k. First of all, it avoid detrimental reaction with radicals. The best reagent also absorb detrimental VUV photons. Etching process can then be implemented on low-k, ensuring good electrical and mechanical properties. The direct application of this work will enable the fabrication of a new generation of more efficient microchips.
Data: CORDIS, © European Union
Project objective
Since the beginning of the electronic evolution, size of transistor never stops to decrease accordingly to Moore’s law. This scaling applies also to the interconnects, composed by conductor and insulating materials, leading to an overall increase of the resistivity of the conductor and the dielectric’s capacitance, ultimately causing delayed signal transmission (so-called RC delay). In order to decrease the resistivity, Al was replaced by Cu as a conductor. The circuit’s capacitance can be lowered by using materials with lower dielectric permittivity, named low-k’s. Nowadays, the most successful low-k dielectrics are porous organo-silicate glasses, with porosity up to 50%, pore size around 1.5-2 nm and k-values down to 1.8 (k=4.2 for bulk SiO2). Interconnects are nowadays built by the Damascene technique, where the dielectric is first deposited, then locally etched away, followed by metal deposition in the patterned structure and polishing for metal excess removal. Due to their intrinsic porosity, most of processing steps cause low-k damage, amongst which plasma etching is the most damaging. The present proposal aims at understanding and optimizing zero-damage cryogenic etching of low-k materials, compatible with the micro-electronics industry (at temperature above -60°C). Besides the improvement of the etching process and the better understanding of reactions damaging the low-k materials during plasma etching, this work will investigate the phenomenon of micro-capillary condensation into porous materials, which is not widely explored and can lead to other applications in micro-electronics and in other nanotechnology domains. This research project will contribute to enable the so-called 5nm node in future CMOS manufacturing, and as a consequence it will have a wide economic impact. Finally, this research will allow the applicant to extend his technical and project management skills, strengthening his profile for a future career in the semiconductor industry or R&D.
Original text from CORDIS.
Participants
- INTERUNIVERSITAIR MICRO-ELECTRONICA CENTRUM · LeuvenCoordinatorBelgium
Links
Data: CORDIS, © European Union