ULPIoT · Ultra-Low Power and Highly-Scalable Interfaces for the Internet of Things
Horizon 2020 — Marie Skłodowska-Curie Actions
- Duration
- 2017-02-01 → 2020-02-28
- EU contribution
- €247,729
- Participants
- 2
- Scheme
- MSCA-IF-GF
Lines connect the coordinator with its partners.
Results in brief
Ultra-Low Power and Highly-Scalable Interfaces for the Internet of Things
Internet of Things (IoT) is the vision of a world where pervasive integrated electronic systems embedded in everyday life objects are fully interconnected to collect, process and exchange useful information. Enabling the IoT requires energy-autonomous systems for distributed sensing and data acquisition. This imposes stringent constraints on cost, size and power for all on-chip sub-systems. The low-cost requirement demands small area, low design effort, digital-like shrinkage across CMOS generations, and design/technology portability. A fully synthesizable Integrated Circuits (ICs) design approach meets all these requirements but is traditionally suitable for digital ICs only. Data processing is digital but most signals from the real-world are analog. The ULPIoT project led by Dr. Orazio Aiello moves towards the idea of re-thinking analog and mixed-signal functions in digital terms, so that to address the fundamental challenges of energy-efficiency, size shrinking, technology portability and reduction of design effort in incoming IoT applications. A novel design approach has been developed, which encompasses the fully automatic synthesis and layout generation of analog and mixed-signal blocks from high-level descriptions (e.g. in Verilog) at minimum effort and by the very same software tools and methodologies adopted in the digital IC flow. This approach leads to IC designs that are natively portable across technology nodes (e.g. from 40nm to 28nm) and highly reconfigurable, thus enabling dynamic energy-quality scaling, which is critical in tightly energy-constrained IoT application scenarios, as well as a low design effort and a fast time-to-market. The project is based on a joint collaboration between the top ASEAN University, the National University of Singapore (NUS, where Dr. Aiello has spent the first two years of his MSCA Fellowship working with Prof. Massimo Alioto) and the Politecnico di Torino (where Dr. Aiello has worked with Prof. Paolo Crovetti). The ULPIoT topic and the related high-quality scientific and technological cooperation with NUS, match with the strategic vision of catching up with the main competitors in ICT research and digital innovation. The possibility to exploit the digital (automated) design flow even for analog building blocks can dramatically reduce the design effort of any system-on-chip that face with an analog signal. The increment of the overall scalability and the higher level of automation in IC design given by a digital-in-concept approach have a straightforward and broad impact on the cost of electronic devices everyone experiences daily.
Data: CORDIS, © European Union
Project objective
The era of the Internet of Things (IoT), in which every physical entity includes power-autonomous embedded electronics, capturing relevant information by sensors and interacting with objects and humans in a globally interconnected network, is bringing about new challenges in Integrated Circuit (IC) design. The performance of ICs in terms of integration density, power consumption and cost, in fact, is the only limiting factor to the feasibility and/or to the widespread diffusion of IoT-based solutions.Digital ICs in the most recent nanoscale CMOS technologies are keeping the pace of IoT requirements. On the contrary, the implementation of analog functions, which are however essential to acquire data from sensors, thus enabling the interactions of IoT nodes with the surrounding environment, is nowadays the real bottleneck and the most serious concern and limiting factor for the further development of IoT applications.In the foreseeable future, the planned device scaling and voltage reduction down to near threshold (e.g. 0.4-0.5V) makes the design of analog circuits extremely hard, in view of the degradation of signal-to-noise ratio, matching and linearity. Despite of device shrinking, traditional low-voltages analog circuits do not really scale down in size, and occupy a more and more relevant percentage (i.e., cost) of the die area.In this scenario, the proposed research activity is intended to substantially enhance the scalability of analog blocks with technology and voltage by re-thinking analog functions in ICs in digital terms. In a new cross-domain approach, design and testing methodologies from the digital world will be extended and frontier design concepts like near-threshold operation further exploited.The effectiveness of the proposed approach will be verified and validated on IC demonstrators and with reference to a full SoC for wearable electronics applications in the development of novel IoT solutions.
Original text from CORDIS.
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Data: CORDIS, © European Union