TPANN · Tensor Processing on FPGAs for Artificial Neural Networks
Horizon 2020 — Marie Skłodowska-Curie Actions
- Duration
- 2017-05-01 → 2018-04-30
- EU contribution
- €93,933
- Participants
- 1
- Scheme
- MSCA-IF-EF-SE
Lines connect the coordinator with its partners.
Results in brief
Tensor Processing on FPGAs for Artificial Neural Networks
Artificial intelligence and, particularly, neural networks are successfully conquering more and more application domains. They help to improve our quality of life and to rid us from repetitive and tedious duties. Their applications range from noise-canceling hearing aids over machine translation to powerful image processing algorithms detecting and classifying objects in real-time video. Albeit amazingly effective, the deployment of neural networks poses an enormous computational challenge. The acceleration by power-hungry GPU farms is the norm rather than the exception. However, neural networks have been shown to be extremely resilient against the quantization of the backing computation to numerical values of harshly constraint ranges. Researchers working with programmable hardware, including the hosting research team of Michaela Blott at Xilinx Ireland, have demonstrated that even binary quantization, leaving only two possible numerical options for each operand, can yield capable neural network implementations in some application domains. The successful quantization of neural network inference is highly relevant as it allows to simplify the backing arithmetic. The platforms that are able to extract benefit from every single saved bit are programmable hardware devices as made by Xilinx. These reprogrammable physical electrical circuits are able to translate simpler operations directly into greater operational density and concurrency. Thus, quantization allows small, power-efficient devices to deploy capable neural networks. Their use becomes a green option and is enabled in more difficult application environments as in embedded or remote contexts or in cyberphysical systems. The goal of TPANN was the rigorous optimization of the neural network inference on programmable hardware devices. Particularly in the ubiquitous convolutional networks, it is the computation of a vast number of dot products that poses a critical challenge. His strong background in digital design and specialization in computer arithmetic of the fellow, Thomas Preußer, was key in this effort. One illustrative result of the work was the development of an object detection demo working on a live video stream running on a small embedded heterogeneous all-programmable device. The work also yielded two invention disclosures that are currently undergoing internal patent review.
Data: CORDIS, © European Union
Project objective
Artificial neural networks have been shown to offer a powerful computing approach to encounter many classification problems as in synthetic vision (e.g. autonomous driving) and artificial intelligence (e.g. AlphaGo). While their implementations are often based on power-hungy CPU- and GPU-installations, first researchers have delivered initial application-specific solutions that demonstrate FPGAs to be a feasible and efficient alternative. This proposal aims at providing a generic reference implementation of ANNs on FPGAs that is tunable towards various application needs by parametrization. Since individual FPGA designs establish enormous costs of entry due to a higher engineering effort on a lower abstration level, an IP core that is available out of the box is a great R&D incentive that enables more researchers and engineers to embrace the emerging efficient heterogeneous computing more quickly and produce innovations and more compact and more efficient products on this basis. Besides this technological advance, this proposal enables a researcher with an enormous experience in mapping computations into FPGA hardware to make a valuable industrial experience in an international context with the major company in this domain. His expertise is ideally complemented with the application experience available at Xilinx who will benefit from opening a new growing market for manufactured FPGA devices. The development of the researcher's skill set is explictly addressed by complementing his academic background with industrial experience and scheduled cooperate trainings. As part of the dissemination activities, his network into the FPGA community is strengthened and approaches towards the ANN community are made.
Original text from CORDIS.
Participants
- XILINX IRELAND UNLIMITED COMPANY · DublinCoordinatorIreland
Links
Data: CORDIS, © European Union