SecuReHLS · EDA tools for Secure and Reliable High Level Synthesis Implementations
Horizon 2020 — Marie Skłodowska-Curie Actions
- Duration
- 2020-09-01 → 2024-02-14
- EU contribution
- €165,085
- Participants
- 1
- Scheme
- MSCA-IF
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Results in brief
EDA tools for Secure and Reliable High Level Synthesis Implementations
In our increasingly digital world, System-on-Chip (SoC) and Internet-of-Things (IoT) technologies are becoming fundamental to enhancing many aspects of daily life, from smart homes and cities to healthcare and automotive applications. These technologies, integrating computational units, sensors, and network capabilities, have the potential to significantly improve our interaction with the surrounding environment by processing and communicating sensitive information. However, the rapid adoption of SoC and IoT devices raises substantial security and reliability concerns. Ensuring the trustworthiness of these devices in handling sensitive data and operating reliably, even in harsh conditions, is imperative for user privacy and safety. The main issue addressed by this project revolves around developing methodologies to concurrently enhance the security and reliability of SoC and IoT devices. Given the critical nature of these devices, it's essential to protect them from both hardware attacks, such as Fault Injection (FI) and Side Channel Analysis (SCA), and environmental threats that could lead to system failures. These challenges are paramount, considering that SoC and IoT devices increasingly process sensitive information and are deployed in scenarios where security breaches or reliability failures could have serious consequences. The project's primary objective was to develop advanced methodologies and algorithms that could be integrated into High-Level Synthesis (HLS) flows used for designing hardware accelerators. These methodologies aim to assess and improve the security and reliability of SoC and IoT devices. The focus was particularly on devices utilizing FPGA technology, due to its flexibility and widespread use in creating specialized computing solutions. In conclusion, the project made important steps towards creating safer and more reliable digital infrastructures. By addressing the dual challenges of security and reliability in SoC and IoT devices, this research contributes towards the deployment of advanced technologies that align with societal expectations for privacy, safety, and trust.
Data: CORDIS, © European Union
Project objective
System on Chip (SoC) and Internet of Things (IoT) hardware accelerators are increasingly used in secure and critical applications, such as medical and automotive. For this reason, they need to have high levels of security and reliability at the same time. Hardware attacks are a serious threat for the security of hardware accelerators. Among them, Fault Attacks and Side Channel Attacks can breach even protected devices. Furthermore, injection of errors due to harsh environments may even lead to catastrophic failures of such accelerators. These threats are usually not concurrently addressed since their corresponding protections are not always compatible to each other. In a context, where designers use High Level Synthesis (HLS) flows to increase the productivity of designing hardware accelerators they must also ensure that security and reliability protections are taken into account by the HLS tools.In order to enable HLS flows to be the flow of choice for secure and reliable devices, we propose to provide to SoC and IoT designers, Electronic Design Automation (EDA) tools, capable to evaluate, improve and automate the insertion of protections during an HLS flow. Initially we will study the effects of HLS flows on the synthesis of manually protected high level descriptions. Afterwards, we will address concurrently security and reliability by automating the integration of compatible, countermeasures and mitigation techniques, inside the HLS flow, so as to automatically obtain secure and reliable RTL descriptions. Such tools and methodologies will help to minimize the corresponding overheads for protecting against each threat, while at the same time they will maintain the productivity of the HLS flow at high levels during the design of secure and reliable hardware accelerators.
Original text from CORDIS.
Participants
- UNIVERSITY OF PIRAEUS RESEARCH CENTER · PIRAEUSCoordinatorGreece
Links
Data: CORDIS, © European Union