SHEPHERD · Cross-layer resilience for rack-scale disaggregated memory
Horizon 2020 — Marie Skłodowska-Curie Actions
- Duration
- 2021-09-01 → 2024-12-30
- EU contribution
- €145,941
- Participants
- 1
- Scheme
- MSCA-IF
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Results in brief
Cross-layer resilience for rack-scale disaggregated memory
The project “Cross-layer resilience for rack-scale disaggregated memory” develops cross-layer resilience techniques to mitigate memory errors in disaggregated memory systems. Disaggregated memory is a memory-centric architecture that separates compute and memory into distinct nodes within a rack, connected by high-performance interconnects. Compute nodes provide processing power, while memory nodes offer large memory capacity, enabling flexible scaling of processing and memory to meet workload demands. This separation enhances memory utilization and scalability by allowing memory to be shared across multiple compute nodes. The project’s overall objective is to address the challenge of memory error tolerance in disaggregated systems, where increasing bit error rates due to memory cell miniaturization and larger number of memory components pose reliability risks. Towards this objective, it develops cross-layer resilience techniques that combine memory protection and replication, with hardware and software working together to efficiently tolerate errors both within individual memory nodes and across nodes in the rack.
Data: CORDIS, © European Union
Project objective
Data-intensive applications, such as search, social connectivity, and e-commerce, are increasingly relying on computer memory for storing and processing a large amount of data with low latency. Emerging disaggregated memory meets this growing demand by leveraging recent technology advances in high-density, byte-addressable non-volatile memory and low-latency interconnects to provide a large memory pool shared across micro-server compute nodes. With a larger memory density and capacity though, memory errors will become more frequent. Addressing such errors becomes paramount as they can cripple service availability and cause data loss. However, established hardware techniques for tolerating memory errors transparently to application software, originally developed for DRAM-based main-memory systems, become impractical at the scale of disaggregated memory due to increasing performance, energy and area overheads. This research will investigate and develop cross-layer memory resilience techniques where software and hardware work together cooperatively to prevent service unavailability and data loss due to memory errors in disaggregated memory with low overhead. It capitalizes on the existing strengths of the experienced researcher (ER) in the area of system software design for non-volatile memory and expertise of the host on memory fault tolerance and micro-server architectures. It will lead to several publications in top-quality venues and will inform forthcoming industrial efforts to develop resilient disaggregated memory micro-server architectures, thus contributing to the research output, visibility, and economy of Europe. Overall, the fellowship will give the ER the opportunity to reintegrate into a long-term academic position in Europe, after a long and fruitful research career in the academic and industrial sectors of the United States. The ER will emerge from the project with new skills and the capability to effectively lead his own research group.
Original text from CORDIS.
Participants
- UNIVERSITY OF CYPRUS · NicosiaCoordinatorCyprus
Links
Data: CORDIS, © European Union