Multi-level synthesis and optimization for reconfigurable hardware

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Project objective

Research objectives and content The objectives of the proposed research include: (a) developing a multi-level framework and tools for automated design synthesis and optimisation, and (b) extending this framework to cover designs involving run-time reconfi- guration. At the lowest level, we plan to improve the development and analysis of library components. At the intermediate level, the low-level information will be used in the selection and parameter instantiation of components for composite designs. For this task, we will explore the use of different constraint-satisfaction techniques. At the highest level, designs will be synthesized from parts of conventional software programs. Additionally, the advantages of run-time reconfiguration will be explored at all levels and integrated in the developed tools. The feasibility of executing analysis and synthesis tasks on-the-fly will be investigated to optimise run-time adaptability and performance. We will evaluate the effectiveness of this approach using case studies of industrial interest. Training content (objective, benefit and expected impact) The project will significantly improve the applicant's knowledge and experience of reconfigurable hardware design. The research group at the host institution is recognised as an international centre of excellence in this field, and it has outstanding expertise in both theoretical and practical aspects of reconfigurable computing not available in the applicant's home country. Links with industry / industrial relevance (22) The host institution has ongoing collaborations with various industrial partners, including Xilinx, Hewlett Packard, Sony, Smith System Engineering, Loughborough Sound Images, and Interval Research. This will provide access to the latest technology and to industrial case studies for this project.

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Participants

• IMPERIAL COLLEGE OF SCIENCE, TECHNOLOGY AND MEDICINE · LONDONCoordinatorUnited Kingdom

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