CMNHFRF · Convergence of microelectronics, nanotechnology and high frequency rf engineering
FP6 — Marie Curie Actions (Human Resources and Mobility)
- Duration
- 2005-04-01 → 2007-03-31
- EU contribution
- €80,000
- Participants
- 1
- Scheme
- IRG
Lines connect the coordinator with its partners. CORDIS does not always give exact coordinates for projects before 2014. These points are placed at city or country level.
Project objective
Passive systems such as inductors, capacitors and transformers, integrated on-chip, are essential building blocks of all analogue RFICs and their performance at current and future CMOS processes is a major bottleneck to successful system integration at the single-chip level radios at high frequencies. Further, this bottleneck prevents a larger-scale integration of more complicated analogue stages essential for wireless communication chips, most notably of filters, which currently remain off-chip. Part of the problem relates to physical properties of standard CMOS processes, i.e., metal and substrate losses and couplings. Another part is the inadequacy of lumped-element design rules for correctly accounting for fully electromagnetic physical effects at high frequencies.Finally, absence of multi-disciplinary research linking the above physical and RF design problems to a synthesis cycle of CMOS-compatible material processes with optimised high-frequency material properties, possibly including composite electromagnetic materials and photonic crystals. This proposal will contribute to remedying these deficiencies in a technologically relevant way, by: First, using novel material Si processes, such as porous Si patterned with high-K or alumina dielectrics, to analyse and optimise the full-wave electromagnetic design of on-chip high-Q passives. It will then use these optimised cells to derive a comprehensive design methodology for on-chip pass-band filters, including accurate broadband circuit models, where the remaining technology process loss will be mapped to the appropriate circuit sub-topologies. Lastly, these losses will be cancelled by the insertion of appropriately optimised FET interconnections of minimum noise figure, to complete a realistic on-chip filter design cycle directly implementable to the semiconductor industry.
Original text from CORDIS.
Participants
- NATIONAL CENTER FOR SCIENTIFIC RESEARCH DEMOKRITOS",INSTITUTE OF MICROELECTRONICS" · AGHIA PARASKEVI - ATHENSCoordinatorCity levelGreece
Links
Data: CORDIS, © European Union
