IMECHIGHK · An advanced electrical characterisation study of alternative gate dielectrics: the effect of charges and defects on material properties

Final Activity Report Summary - IMECHIGHK (An advanced electrical characterisation study of alternative gate dielectrics: the effect of charges and defects on material properties)

The objective of this project was to gain an advanced understanding of the defects which exist in high-k dielectric materials used in modern CMOS devices, and to develop new techniques by which to characterise the behaviour of these defects. In order to achieve this goal, we approached the project from a number of angles. Firstly we employed the substrate hot electron injection (SHEI) technique to gain a fundamental understanding of the electron energy dependence of defect generation in dielectric layer, and showed for the first time that high energy electrons in the substrate which are injected over the oxide energy barrier primarily create traps in the bulk of the high-k layer, while lower energy electrons primarily create interface traps in the interfacial SiO2 layer. This work was presented at SISC 2007 and published in the Journal of Applied Physics. To further our understanding of both the physical position of the created defects and their position in the dielectric energy gap, we developed a novel spectroscopy method using the Stress Induced Leakage Current (SILC) through the layers, which measures defect generation by comparing the initial gate current with the post-stress gate current. Normally SILC is sensed at a single voltage; however, expanding the measurement to sense across the low gate-voltage range allows characterisation of both the physical position of the defects and their energy position in the band gap. The technique can be used as a simple, on-the-fly method to measure the generation of both interface and bulk defects during electrical stress. A paper on the technique was presented at the International Reliability Physics Symposium (IRPS) 2008 with the highest score for the high-k section. Further work where we have used the technique to analyse the effect of specific processing parameters on the defect generation has been accepted to IRPS 2009 and a journal contribution is in preparation. A high temperature spectroscopic SILC study has also been initiated in the group. Another major branch of the project is in gaining an understanding of Bias Temperature Instability (BTI) in dielectric layers, whereby the threshold voltage of MOSFETs tends to shift after a voltage stress. A theoretical work on the permanence of damage to the oxide associated with BTI was presented at the 2007 International Electron Devices Meeting (IEDM) and another at IRPS 2008 and the (Workshop on Dielectrics in Microelectronics) WoDiM 2008. Our activity also involves supporting the process development groups and our work on BTI behaviour in novel gate stacks featured in 2 papers presented at IEDM 2007. The final goal in the BTI branch of the project is the understanding of how the degradation mechanisms change under AC stress, when compared to conventional DC stress measurements. We have carried out a study which shows that the BTI behaviour is completely independent of frequency in the range up to 2GHz. In summary, the project has significantly advanced the understanding of the defect generation in high-k materials and led to the development of new materials analysis techniques which are becoming widely used in the field.

Data: CORDIS, © European Union