PSYCHES · Predictable synchronous components for high-performance embedded systems
FP6 — Marie Curie Actions (Human Resources and Mobility)
- Duration
- 2006-03-01 → 2009-02-28
- EU contribution
- €16,856,062
- Participants
- 4
- Scheme
- TOK
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Results in brief
Final Activity Report Summary - PSYCHES (Predictable synchronous components for high-performance embedded systems)
The PSYCHES project is dedicated to the creation of an intermediate language extending scalar data-flow with the notion of timestamps. Its main goal is to improve the ease of programming, the compilation and optimisation of parallel streaming applications. The collaboration between NXP, INRIA and UPC allows work on three different aspects of the project: language theory, compilation and architecture. During the first two years, the project has mainly focused on the development of its theoretical part and its validation. During the third year, the work was centred on the compilation part and on the development of an execution framework. The complexity of the task was underestimated at the beginning of the project, and it took more time than expected. Therefore, not enough time has remained to work on the hardware implementation part. Hence, the visits between the partners have mainly taken place between NXP and INRIA. However, even if there were no effective secondments with UPC, there were several exchanges (1 or 2 days every 3 months in average) and communication. During the first two years of the project, the different collaborations have led to three different outcomes: - The first one is based on the relaxation of the clocks in the synchronous paradigm. The purpose is to take into account the time jittering of video streaming applications. This work has started during the visit of Marc Pouzet (INRIA and Paris-Sud University) at NXP and is still developed by Florence Plateau (INRIA) as abstract clocks for the N-synchronous model. - The second topic is based on the notion of burstiness and was inspired by the variability of the production of data blocks in video streaming applications. It has mainly been discussed by Albert Cohen (INRIA), Marc Duranton (NXP) and Philippe Dumont (PSYCHES post-doc at NXP). - The third topic is dedicated to the proposition of a new model of computation and communication (MoCC). This model aims to be generic in the sense that usual models can be translated in this new one (Synchronous, but also KPN, CSP,...). This work is issued from the collaboration of Marc Duranton, Albert Cohen and Philippe Dumont. During the third year, the work was centred on the practical implementation of the last two topics. The notion of 'burstiness' has been introduced in the synchronous paradigm to represent groups of activation. It leads to the notion of integer clocks. It was studied by Leonard Gerard (INRIA) during his master thesis with the help of Albert Cohen and Marc Pouzet. He continues this work in a PhD which has started on September 2008. The notion of burstiness can also be applied to the compilation of streaming applications. This notion has been used to create an intermediate representation which is designed to ease the optimisation at compilation time, but also to check static properties (determinism, deadlock freeness, bounded memory) under some restrictions. The execution is done thanks to a platform specific runtime library to maximise the performances. An implementation and a few examples have been developed by Cupertino Miranda (INRIA) and Philippe Dumont. These results of the Psyches projects are used as underlying mechanism to validate and simulate applications developed with two higher level languages. The first one is LIME: a C+XML language based on the CSDF MoCC developed by Ptjor Koursanov (NXP). The second one is SPM (Streaming Programming Model) of the European project ACOTES (please see http://www.hitech-projects.com/euprojects/ACOTES/ online). LIME and SPM provide a convenient way to code in parallel applications which are executed on our runtime library. The work on the new MoCC (third topic) has been continued. A first formalisation has been realised based on the Turing machine representation and was later complemented by another formalism used in the synchronous domain. The model is now powerful enough to enclose several other models of concurrency and will be published in the mid/end of 2009.
Data: CORDIS, © European Union
Project objective
The TOK-IAP PSYCHES project will allow to build knowledge for the development of low cost, high performance highly parallel architecture and methodology for the high demanding video consumer appliances, closing the gap between the performance density of dedicated hardware and the flexibility of programmable approach. The research project, build from the exchange of knowledge between Philips, INRIA and UPC, relies on the following key research aspects:- A sound, theoretical model allowing to build systems and software correct by construction". - A compiler technology allowing extracting wide parallelism from domain specific applications. We believe that in the domain of embedded video processing this can be achieved with state-of the art technique developed in INRIA and UPC. - An efficient communication infrastructure or memory hierarchy, allowing to feed a high number of compute units simultaneously. - An optimised, but yet open to a wide variety of applications in the video processing domain. We advocate that, provided we strike the right balance between the architecture, compiler and user effort, it is possible to unveil multi-grain parallelism and to take advantage of it without excessively complex architectures or compilers. As seen, the multidisciplinary approach is mandatory to the success of the project, and the various cultures of the participants - industrial (Philips), theory and compilation (INRIA), architectures (UPC)- is the strong point for this Transfer Of Knowledge. The true complementarities of Philips, INRIA and UPC will be necessary to successfully follow this approach that will pave the way to new research projects that will bring a new family of systems that could outperform the US dominated microprocessors for high performance embedded consumer applications, giving to Europe a leading edge in this market."
Original text from CORDIS.
Participants
- NXP SEMICONDUCTORS NETHERLANDS BV · EINDHOVENCoordinatorNetherlands
- INSTITUT NATIONAL DE RECHERCHE EN INFORMATIQUE ET AUTOMATIQUE, UNIT??????A? DE RECHERCHE FUTURS · LE CHESNAYCity levelFrance
- PHILIPS ELECTRONICS NEDERLAND B.V. · EINDHOVENNetherlands
- UNIVERSITAT POLITECNICA DE CATALUNYA · BARCELONASpain
Links
Data: CORDIS, © European Union
