ADAGIO · ADAptive circuit techniques for current-mode ultra low-power diGItal Integrated Circuits

ADAptive circuit techniques for current-mode ultra low-power digital integrated circuits

Project objectives The fundamental project objectives concern the development of innovative design methodologies and power management techniques to design reliable ultra-low power digital circuits. These objectives are pursued at various levels of abstraction, from circuit to system level, as well as from the perspective of design automation based on commercially available CAD tools. In particular, from the circuit standpoint, the main objective is to devise innovative adaptive circuit techniques for ultra-low power to meet the requirements imposed by the energy budget and constraints in real applications. In particular, innovative circuit techniques are to be developed to enable effective and energy-efficient tuning to track the minimum energy point or some other targeted point in the energy-performance space. Smart and aggressive power management strategies are investigated. In particular, heavy duty cycling is exploited to dramatically reduce the energy/power consumption of VLSI systems. At the system level, power management techniques that efficiently fit existing communication protocols for wireless nodes or tags (e.g. ISO/IEC 18000-7) are also investigated. Work performed since the beginning of the project In the first year of the project, various activities were executed, as described in the following. By taking advantage of the strong expertise of UC Berkeley in CAD tools and design flows, commercial CAD tools were assembled into a digital design flow by writing appropriate scripts. Prototype circuits that were previously implemented at BWRC were reviewed and analysed to understand energy/speed typical budget, power-down policies, interaction between blocks in real applications and identify a set of hardware energy-critical operations. Circuit analysis of basic logic gates was also performed for the sake of characterisation in terms of performance, energy and sensitivity to process/voltage/temperature variations. A small MCML standard cell library was designed and characterised in terms of timing, energy, area, and related library files were generated for synthesis/place and route tools. Finally, a test chip was taped out to implement the above described power management strategies. Main results achieved so far The main results of the first year of the project are listed in the following: - A complete design flow was defined by using only commercial CAD tools, and appropriate scripts were written to fully integrated these tools. - Typical scenarios were widely explored and understood from measurements on prototypes that were available at BWRC in the context of real applications. - The effectiveness of the considered power-down policies was assessed through measurements of previously developed prototypes that were controlled by a commercial AMX wireless platform. - The occurrence of commands and their impact on the energy consumption were evaluated through measurements on prototypes by using the above-mentioned AMX platform. - The most critical logic gates in terms of energy efficiency and sensitivity to process/voltage/temperature variations were identified through circuit-level characterisation of developed standard cells. - An integrated prototype was taped out to validate the above power management strategies, which were implemented by using the above described design flow. Expected final results and their potential impact and use The research activity defined by this project aims at developing techniques and methodologies to design ultra-low power VLSI circuits for wireless sensor nodes. The results are expected to have a strong impact on the energy efficiency of sensor nodes and hence on all related applications, such as biomedical engineering, building monitoring, asset management, local positioning systems, retrofitting existing equipment for smart and remote power management.

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