CNTCONTACT · Doped semiconductor contacts for low resistance contacts to carbon nanotubes

Doped semiconductor contacts for low resistance contacts to carbon nanotubes

Intensive research and development work on carbon nanotubes (CNTs) has been ongoing for over a decade, whereas commercial products available for exploitation by society are limited. Products on the market typically feature CNTs in composites for lightweight reinforced structural materials, taking advantage of the highly desirable mechanical properties of nanotubes. The CNTs used for these purposes do not need to have good electrical properties, and can be mass produced cheaply. In contrast, making nanotubes available for consumer electronics (processors, memory devices) and niche electronics (ultrasensitive sensors, very low power devices) applications will require pristine, single walled CNTs where the electrical properties are as close to the theoretical best values as possible. The properties to consider include carrier mobility, which is affected by not only the defect density on the tube itself, but also its interfaces with the environment. This project focused on optimizing process flows for carbon nanotube based transistor in order to achieve low contact resistances and high device performance. The main points to consider were the stability of the materials used, preservation of the high quality CNTs throughout the process, and scalability of any developed process to a large enough scale for commercial applications. While there are several obstacles remaining in the way to having practical commercial products featuring CNTs, this project contributes to our understanding and coping with a key challenge: having a pristine nanotube at the end of the process flow. Very often, nanotubes are exposed to a variety of chemicals and harsh treatments throughout the fabrication process of a transistor. These include was photoresists, plasma cleaning steps and oxidation. The approach taken in this project was to invert the flow of the conventional transistor fabrication process, thus making the nanotube growth the last step executed. In this way, the CNT came into contact with none of the chemicals nor the cleaning procedures. The results present a process for transistor structures, as well as an evaluation platform for arbitrary post-processing and coating experiments. The resulting process is a 2-mask, photolithography based fabrication flow, using deep-UV illumination and image reversal to achieve small features (down to 1.6 µm). Batch fabrication of hundreds of transistors is possible at chip level, and scaling up to wafer level is foreseen to yield thousands of transistors per run. In its current state, the process takes 4 days to complete from blank wafer to transistors. The results demonstrated through the project are: a process flow that yields ultraclean carbon nanotube transistor stuctures, and a platform for evaluating the effects of specific treatments on structural and electrical properties of nanotubes. The platform can be a basis for controlled experiments for isolating and understanding the way specific processing steps (such as exposure to chemicals, plasma, various atmospheres) change transistor behavior. Additionally, it can be used for studying transport properties in nanotubes and sensing mechanisms in gas sensors based on CNFETs.

Data: CORDIS, © European Union