HEИндивидуална стипендия2023–2026

ACROBAT · Hardware Acceleration with Tunable SRAM/IMC Voltages

„Хоризонт Европа“ — Действия „Мария Склодовска-Кюри“

Период: 2023-09-01 → 2026-08-31
Финансиране от ЕС: 239 283 €
Участници: 3
Схема: HORIZON-TMA-MSCA-PF-GF

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Накратко на български

Специализирана памет (SRAM) с регулируемо напрежение се изследва, за да се оптимизира работата на невронни мрежи. Това помага за намаляване на консумацията на енергия и подобряване на стабилността на устройствата с изкуствен интелект.

Този кратък обзор е генериран от изкуствен интелект

Кратко обяснение, генерирано от езиков модел по текста на CORDIS. Оригиналът е по-долу.

Резултати накратко

Hardware Acceleration with Tunable SRAM/IMC Voltages

In this project, an automatic memory design framework employing a specialized SRAM with tunable voltage levels is proposed to reduce energy consumption and alleviate the search complexity of the design space. The study is then planned to be extended to the emerging in-memory computing (IMC) design and suggests a solution to solve the common SNR and robustness problems in this research area. The framework outputs the optimal set of memory configurations for a given DNN workload. It accounts for the integration of different algorithmic optimizations while balancing the accuracy and the SRAM/IMC energy consumption and fault rates with reconfigurable weight precision. This improvement is important as IMC design is considered one of the most promising approaches to energy efficiency in the edge-AI era, where there is high demand both in industry and academia to come up with innovative, robust architectures, and power-efficient end products. [The implementation is not completed due to the early termination of the project (end of work date on January 12, 2024).]

Текст от CORDIS, на английски · Данни: CORDIS, © Европейски съюз

Цел на проекта

Deep Neural Networks (DNNs) are the fundamental component in most artificial intelligence applications. With the increasing number of applications based on artificial intelligence, the performance and energy efficiency of architectures running these algorithms have become crucial, especially for battery-powered platforms. In this work, I propose an energy optimizing memory design framework with a special SRAM/in-memory-computing structure. It also utilizes datapath optimization techniques like quantization and pruning with a fine-level assignment. Compared to other hardware accelerator studies for DNN processing, in this work, I will show that this special memory design, together with the architectural datapath optimization techniques, will have a much better capability of finding the Pareto optimal point in the energy-accuracy trade-off and increase the profitability of the final design.

Оригинален текст от CORDIS (на английски).

Участници

BILKENT UNIVERSITESI VAKIF · Bilkent AnkaraКоординаторТурция
MASSACHUSETTS INSTITUTE OF TECHNOLOGY · CambridgeСъединени щати
STMICROELECTRONICS CROLLES 2 SAS · CrollesФранция