EASIFeT · Energy-efficient Artificial Synapses based on Innovative Ferroelectric Transistors

Energy-efficient Artificial Synapses based on Innovative Ferroelectric Transistors

The fast development and extensive use of powerful generative Artificial Intelligence models is causing a massive increase in the demand of computing power for data processing. The training of AI models, which often have billions of parameters, requires a staggering amount of electricity and comes with serious environmental consequences, including increased carbon dioxide emissions and water consumption, besides putting the electric grid under severe stress. Data centers already consume roughly 1.5% of global electricity, and the International Energy Agency predicts that this figure could double by 2030, reaching a level of consumption comparable to that of the entire country of Japan. This calls for a new way of designing computing systems to overcome the "bottleneck" of traditional computers, which physically separates the processing unit from the memory unit and forces data to constantly travel back and forth between the two, limiting the performance and energy efficiency of the entire system. A paradigm switch to data-centric platforms, with the co-localization of processing and memory functionalities, would be thus highly beneficial. Neuromorphic computing addresses this challenge by developing low-power computing chips that mimic the brain's structure, which leverages distributed computing in artificial neurons and localized storage in artificial synapses and drastically reduces the need for constant data transfer. Neuromorphic chips have the potentiality to not only reduce global energy consumption but also enable "edge computing", allowing mobile devices, medical sensors, and autonomous vehicles to process complex data directly on a local hardware, rather than relying on distant, power-hungry data centers. The development of highly energy efficient artificial synapses represents a crucial step for the realization of neuromorphic circuits. An artificial synapse is a nanoelectronic component designed to mimic the functions of a biological synapse, i.e. the connection between neurons. In the human brain, information is passed between neurons through a synapse: the strength of this connection is the synaptic weight. A strong weight means the signal passes easily, whereas a weak weight means the signal is nearly blocked. Thus, the most critical function of an artificial synapse is the ability to exhibit plasticity, meaning that the synaptic weight (usually electrical conductance) can be modulated by incoming electrical signals. Among the different technological implementations of artificial synapses, ferroelectric devices are emerging as promising candidates due to their high energy efficiency and compatibility with standard CMOS circuit processing. Their development started with the recent European discovery of ferroelectricity in hafnium oxide. Ferroelectric materials, in particular hafnium zirconium oxide, contain microscopic electrical dipoles, due to the non centro-symmetric nature of the unit cell. Each dipole has two possible orientations, i.e., it can either “point up” or “point down”, and it can be flipped by an applied electric field, thus acting as a stable, non-volatile switch. EASIFeT project investigated, by means of analytical and numerical simulations, a specific ferroelectric device, namely a Ferroelectric Schottky Barrier Field Effect Transistor (Fe-SBFET), as an artificial synapse for neuromorphic computing. This device is particularly interesting because it can be fabricated in the back-end-of-line (BEOL) of CMOS circuits (i.e., on top of standard chips with a 3D integration), and it features at least three terminals, thus making it possible to decouple write and read operations. The objectives of this study were: a) the development of a TCAD framework for the numerical simulation of such devices; b) the use of TCAD simulations to identify optimization strategies for energy efficient artificial synapses; c) the development of compact models for circuit-level simulation of the Fe-SBFETs.

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