BECKSDIMA2003 · MEMS/Porous-Silicon to MCM-D Technology Matching

Final Activity Report Summary - BECKSDIMA2003 (MEMS/Porous-Silicon to MCM-D Technology Matching)

The project aimed at bringing together on a single module different technologies. 1) MEMS to MCM-D Technology Matches - it has been observed in previous work that MCM-D modules with large numbers of data processing chips (16) may be noisy due to the digital activity of the chips. This is damaging to the analogue signals and needs to be eliminated. Usually this is achieved with decoupling capacitors. As voltages shrink and currents grow, the resistance to the decoupling capacitors prevents the decoupling scheme to work. An alternative is to use inductors in series with each individual chip. The larger the currents, the smaller the inductors need to be. A problem with inductors however is their LdI/dt swing. This has been solved with 'local' capacitors in parallel with the chips. The solution was SPICE simulated and characterised in view of the evolution of technology towards 60 nm and 45 nm. The paper was accepted in the Nuclear Instruments and Methods - A (tracking nr. NIMA44413 - now in print). A Demonstrator was realised on PCB, the inductors being discrete SMD components (Murata). The measurements on the Demonstrator confirm the idea. A second Demonstrator, on a Silicon wafer was built with on-chip inductances. The latter were at design inductance (ca. 980 nH), however had a rather small Q factor of 1.4 due to capacitive coupling to the substrate. The results were presented and published in Proceedings at the IEEE International Semiconductor Conference CAS-2005. The fellow was trained in the many aspects OrCAD and CADENCE design, and in SPICE simulations with real-world technologies (IBM-7RF). He improved his working skills with digital and analogue equipment on the Karl-Suss test-bench. 2) Porous-Silicon to MCM-D Technology Matches - similarly, the aim was to include Porous-Silicon technology on MCM-D modules. To prove the idea a Demonstrator was build, with a Porous-Silicon substrate gas sensor attached to circuitry structure above it. The fellow was trained in the many aspects of Porous-Silicon technology, SnO2 sol-gel technology for the active gas-sensing layers and their characterisation methods. The fellow developed an EDX analysis software. The matching solution found was Al/SiO2/SnO2/Si-porous/Si, this providing the good adherence needed on SnO2 (which in its vitrified form rejects many metallisations). Gas-sensing chips were encapsulated in TO-72 cases and subjected to detailed electrical tests in H2 and O2 environments vs. temperature, concentration and substrate. The results confirm the better sensitivities of Porous-Silicon substrate chips and surprised with a comparable (or better) recovery time. The 'inversion' temperature for Porous-Silicon substrate chips was lower, and likewise their nominal working temperatures for maximum sensitivity. The results were presented and published in Proceedings at the IEEE International Semiconductor Conference CAS-2005.

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