VECTORMULTIPROCESSOR · Vector Multiprocessor architecture for multimedia energy-efficient applications
6РП — Действия „Мария Кюри“
- Период
- 2005-08-01 → 2006-07-31
- Финансиране от ЕС
- 151 854 €
- Участници
- 1
- Схема
- EIF
Линиите свързват координатора с партньорите.
Накратко на български
Архитектурата на векторни многопроцесори се изследва чрез оптимизиране на обработката на видеото по стандарта H.264. Това помага за създаването на по-енергоефективни и бързи устройства за възпроизвеждане на видео с висока разделителна способност.
Кратко обяснение, генерирано от езиков модел по текста на CORDIS. Оригиналът е по-долу.
Резултати накратко
Final Activity Report Summary - VECTORMULTIPROCESSOR (Vector Multiprocessor architecture for multimedia energy-efficient applications)
This work investigated the suitability of a vector coprocessor tightly coupled to a reconfigurable scalar core as an optimal platform to support high performance video coding. After a thorough review of state of the art hardware architectures for video coding, the research analysed the computational demands of the latest standard for advanced video coding, namely the H.264 AVC algorithm which was also known as MPEG4 part 10. The STMicroelectronics implementation of H.264 was ported to the STxP70 scalar reconfigurable processor and its instruction set extended to target video coding applications. A complete vector instruction set architecture (ISA) and vector microarchitecture were proposed as generic high-performance extensions for scalar processors and their benefits were evaluated using cycle accurate architectural simulators. A dedicated accelerator was then proposed to target the complex task of arithmetic entropy coding in H.264, which proved not to be well suited for the data level parallelism exploited by vector architectures. The flexibility of the STxP70 core enabled this option as long as the hardware extensions, either vector or dedicated, were mapped to a reconfigurable fabric which could change its functionality depending on the loaded bitstream. The combination of reconfigurable processor and fabric formed the fundamental processing element with excellent scalable properties. Finally, a proposal of how an array of these high-performance processing elements could be connected together was made in the form of a network-on-chip implementation that should provide the multiprocessing capabilities needed in current and future high-definition video products.
Текст от CORDIS, на английски · Данни: CORDIS, © Европейски съюз
Цел на проекта
The past 10 years have witnessed an explosion of the amount of visual information that must be transmitted and stored efficiently using limited and expensive resources. Advanced video coding that allows orders of magnitude reduction in the required bit-rates is regarded as an enabling technology to move personal communications to a higher level of interactivity. Common features required in personal communication systems are the need for high-quality, low bit-rate video coding implemented in high-performance, low energy consumption and low design complexity hardware platforms. This work aims to research novel embedded CPU architectures that will enable the acceleration of video coding applications in wireless networks by studying the feasibility of a vector multiprocessor architecture. The combination of several vector units running different threads of the same codec has significant potential in achieving leading area/power/cost metrics in real-time video-encoding. Vector Multiprocessing hardware is expected to enable the transmission of high-quality low-bit rate video content in current and next-generation networks and will contribute to make video content transmission as inconspicuous as voice transmission is today. The following clear objectives apply to this research: 1.Evaluation of the amount of data-level and thread-level parallelism in current and emerging video coding standards and specification of a suitable vector ISA for the proposed workloads. 2. Investigation of the micro-architectural parameters for the optimal multimedia vector pipeline coupled to a controlling CPU. 3. Investigations into the memory subsystem, processor interconnection and the specialization of the vector pipeline to support the algorithm threads in the multiprocessor platform. 4. Implementation of the vector multiprocessor SoC using a state of the art ASIC or equivalent FPGA technology.
Оригинален текст от CORDIS (на английски).
Участници
- STMICROELECTRONICS S.R.L. · AGRATE BRIANZAКоординаторИталия
Връзки
Данни: CORDIS, © Европейски съюз