FUNC · Fundamental understanding of novel materials integration in future CMOS
6РП — Действия „Мария Кюри“
- Период
- 2004-09-01 → 2008-08-31
- Финансиране от ЕС
- 15 102 400 €
- Участници
- 2
- Схема
- TOK
Линиите свързват координатора с партньорите. За проекти отпреди 2014 г. CORDIS не винаги дава точни координати. Тези точки са на ниво град или държава.
Накратко на български
Нови материали, като германий и полупроводници от III-IV група, се изследват като алтернатива на силиция за създаване на по-малки транзистори. Това е важно, за да се увеличи производителността и скоростта на бъдещите електронни устройства.
Кратко обяснение, генерирано от езиков модел по текста на CORDIS. Оригиналът е по-долу.
Цел на проекта
The Si-based Complimentary Metal-Oxide-Semiconductor Field-Effect Transistor technologies (CMOS FET) are the foundation of the electronic industry. However, the continued scaling of the MOSFET device below the 45nm technology node (sub-20nm gate lengths, expected in production after 2007) will require fundamental changes in the CMOS processing and the introduction of new materials. It is notable however, that so far all the efforts of the industry to replace Si-SiO2 system with Si-High-k one have failed, pointing towards the fundamental issues of such replacement.In addition, the roadmap requires an increase in device performance associated with extra improvement in mobility/transconductance for sub-25nm MOSFETs. Such performance increase should be as large as 100% for the smallest generations and can be achieved with alternative channel materials (e.g., Ge and most III-IV semiconductor compounds have inherent electrical advantages over Si, such as a higher electron mobility and/or breakdown voltage). There is a strong need exists to examine thoroughly the key parameters that will allow the introduction of such new materials in future CMOS devices. It is the purpose of this project to study in detail the fundamental possibilities for CMOS scaling provided by novel materials.The work will be separated into the following sub-topics:- Modeling of Semiconductor-Dielectric-Gate electrode interfaces in future FET devices- Process and Device modeling of Alternative to Si channel materials compatible with Si CMOS processingThe fundamental understanding achieved on the basis of these studies will be used to demonstrate MOSFET devices in sub-25nm gate-length regime suitable for future CMOS integration activities.
Оригинален текст от CORDIS (на английски).
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Данни: CORDIS, © Европейски съюз